In reply to ben@SystemVerilog.us:
I have a doubt in it. If we use @(posedge BRCLK) ##[0:7] $rose(INST), Wont the assertions checks for rising edge of INST within 0-7 PCLK cycles, instead of BRCLK.
Can you please look into the below code, as respective clocks will be considered within the bracket/Sequence:
@(posedge PCLK) $fell(TX) |->
(@(posedge BRCLK) ##[0:7] $rose(INST));
Please correct me if I am wrong.