Clocks donot agree in cycle delay operator in sequence operator: assertions

SystemVerilog
,
1

hello,
we r getting following error for:
property p1;
@(posedge PCLK) $fell(TX) |-> @(posedge BRCLK) ##[0:7] 1) ##0 $rose(INST);
ENDPROPERTY

       here we r trying to sample TX for low and after it is low after 0 -7 BRCLKS which is another clock we need to sample INST.

       please provide kind feedback.
       error: clocks donot agree

thanks
raman

2

In reply to ramandeepk:


property p1;
@(posedge PCLK) $fell(TX) |-> 
 @(posedge BRCLK) ##[0:7] $rose(INST);
endproperty

Ben systemverilog.us

3

In reply to ben@SystemVerilog.us:

Hi,

I have a doubt in it. If we use @(posedge BRCLK) ##[0:7] $rose(INST), Wont the assertions checks for rising edge of INST within 0-7 PCLK cycles, instead of BRCLK.

Can you please look into the below code, as respective clocks will be considered within the bracket/Sequence:

property p1;
@(posedge PCLK) $fell(TX) |->
(@(posedge BRCLK) ##[0:7] $rose(INST));
endproperty

Please correct me if I am wrong.

Thanks,
Lithin

4

In reply to lithinbalu:

Bracket doesn’t make any difference in this case.

Example to understand the different:

	
// a sampled at clk1 , b and c sampled as clk2, basically clk2 flows if it isn't parenthesized  	
@(posedge clk1) (a) |-> @(posedge clk2) b ##1 c;


// a sampled at clk1 , b sampled as clk2 and c sampled as clk1,
// clk2 flow is restricted only for b 	
@(posedge clk1) (a) |-> (@(posedge clk2) b) ##1 c;