Clocking block /assignment of output

SystemVerilog
,
1

I have a clocking block defined in the interface file for the inputs and outputs of DUT.

For every request that the DUT sends to block A, block A responds with an ack. And when both request && ack are high, the request is considered valid. And for every request, I need to send one valid+one data to DUT.

Since the i/ps and o/ps are defined in a clocking block, I need to use <= when I want to drive valid/data. This causes my valid and data to always last one clock cycle longer than necessary.

Is there a way I can avoid this? Does this have anything to do with how I define the default timing inside clocking block. Example for a 2ns clock, I define : default input #10ps output #10ps;

Thanks.

2

In reply to UVM_learner6:

Inside the send task of the uvm driver, I cannot use assign statement inside this block because variables accessed through VIF cannot be used in continuous assignments . If I use <= non blocking, it extends the valid by one extra clock which I do not want.

              if(vif.cb.o_req_w && vif.cb.i_ack_w) 
              begin
                vif.cb.i_rid_w   = vif.cb.o_id_w;
                vif.cb.i_rid_w   <= vif.cb.o_id_w; 
                vif.cb.i_rvalid_w <= 'b1; 
                vif.cb.i_rdata_w  <= req.i_rdata_w;
                vif.cb.i_rerr_w  <= req.i_rerr_w;
              end