Clocking block issue

Hey,

I am trying to modify a code to work with clocking blocks, this is my first time and I am struggling to understand my issue.

What I get is the following messages “Variable ‘/YcbcrTB/YcbcrTopVif/YcbcrMasterVif/tready’, driven via a port connection, is multiply driven. See …/YcbcrTestBench/YcbcrTB.sv(62).”
lots of them, everything that is an input to the clocking block to be more specific.

What am I misunderstanding here?

I am attaching the relevant parts of the code for further understanding.

top interface:__

interface YcbcrTopIf (
			input [256*8-1:0] config_db_name,
			input AxiClk,
			input reset
			);
		

		import uvm_pkg::*;
		`include "uvm_macros.svh"
		import ParametersPkg::*;
  

		YcbcrIf#(.DATA_WIDTH(ParametersPkg::DATA_WIDTH)) YcbcrMasterVif(
				.Clock(AxiClk),
				.config_db_name("YcbcrMasterVif"),
				.Reset(reset)
			);

		YcbcrIf#(.DATA_WIDTH(ParametersPkg::DATA_WIDTH)) YcbcrSlaveVif(
				.Clock(AxiClk),
				.config_db_name("YcbcrSlaveVif"),
				.Reset(reset)
			);
		
 
		//===========================================================
		//     Registration the interface into uvm_config_db
		//===========================================================
		initial begin
			@(config_db_name);
			uvm_config_db#(virtual YcbcrTopIf)::set(uvm_root::get(),"",string'(config_db_name), interface::self());
		end
endinterface : YcbcrTopIf

relevant part of testbench:__

RGB_422_Top dut(
			//Control ports
			.aclk(AxiClk),
			// Ask Ruvik how is he using this signal
			.aresetn(SysReset),
			.s_axis_video_tdata(YcbcrTopVif.YcbcrMasterVif.tdata),
			.s_axis_video_tready(YcbcrTopVif.YcbcrMasterVif.tready),
			.s_axis_video_tvalid(YcbcrTopVif.YcbcrMasterVif.tvalid),
			.s_axis_video_tlast(YcbcrTopVif.YcbcrMasterVif.tlast),
			.s_axis_video_tuser_sof(YcbcrTopVif.YcbcrMasterVif.tuser),
			.m_axis_video_tdata(YcbcrTopVif.YcbcrSlaveVif.tdata),
			.m_axis_video_tvalid(YcbcrTopVif.YcbcrSlaveVif.tvalid),
			.m_axis_video_tready(YcbcrTopVif.YcbcrSlaveVif.tready),
			.m_axis_video_tlast(YcbcrTopVif.YcbcrSlaveVif.tlast),
			.m_axis_video_tuser_sof(YcbcrTopVif.YcbcrSlaveVif.tuser)
							   
		);

Master/Slave Interface:__

interface YcbcrIf #(parameter DATA_WIDTH) (input Clock, input Reset, input [256*8-1:0] config_db_name);

	//Interface Signals
	logic SysReset; 
	logic [DATA_WIDTH-1:0] tdata;
	// Ready
	logic tready;
	//Valid
	logic tvalid;
	//EOL
	logic tlast;
	// SOF
	logic tuser; 
	
	// Debug Bits
	bit CompareError;
	int PixelCounterIn;
	int PixelCounterOut;
	bit signed[10:0] Red, Blue, Green;
	bit [DATA_WIDTH-1:0] ExpectedDataOut;
	
	
	//Modports
	//modport YcbcrMasterDriverModPort(input Clock, input tready, input Reset, output SysReset, output tdata, output tvalid, output tlast, output tuser, output Red, output Green, output Blue);
	//modport YcbcrSlaveDriverModPort(input Clock, input Reset, input tvalid, input tdata, input tuser, input tlast, output tready);
	modport YcbcrMonitorModPort(input Clock, input Reset, input tready, input tdata, input tvalid, input tuser, input tlast);
	modport YcbcrMasterDriverModPortCb(input Clock, input Reset, clocking clockingBlockMaster);
	modport YcbcrSlaveDriverModPortCb(input Clock, input Reset, clocking clockingBlockSlave);
	
	
	clocking clockingBlockMaster @(posedge Clock);
		default input #1step output #1step;
		output tvalid, SysReset, tdata, tlast, tuser, Red, Green, Blue;
		input tready;
	endclocking
	
	clocking clockingBlockSlave @(posedge Clock);
		default input #1step output #1step;
		input tuser, tvalid, tlast, tdata;
		output tready;
	endclocking

	// Inteface Database self setting
	import uvm_pkg::*;
	initial begin
		@(config_db_name);
		uvm_config_db#(virtual YcbcrIf#(DATA_WIDTH))::set(uvm_root::get(),"",string'(config_db_name), interface::self());
	end
endinterface

relevant part MasterDriver:[u][/u]

task YcbcrMasterDriver::driveSignals(YcbcrSequenceItem#(DATA_WIDTH) req);
	`uvm_info(get_type_name(), $psprintf("driveSignals Starting"), UVM_DEBUG)
	fork
		begin
			YcbcrMasterDriverVif.clockingBlockMaster.tuser<= (req.tuser == 0) ? (YcbcrMasterDriverVif.clockingBlockMaster.tvalid && 
                        YcbcrMasterDriverVif.clockingBlockMaster.tready) ? req.tuser : YcbcrMasterDriverVif.clockingBlockMaster.tuser : req.tuser;
			repeat(req.tuserNumOfCyclesDelay) @(YcbcrMasterDriverVif.clockingBlockMaster);
		end
		begin
			YcbcrMasterDriverVif.clockingBlockMaster.tvalid <= req.tvalid;
			repeat(req.tvalidNumOfCyclesDelay) @(YcbcrMasterDriverVif.clockingBlockMaster);
		end
		begin
			if(YcbcrMasterDriverVif.clockingBlockMaster.tvalid && YcbcrMasterDriverVif.clockingBlockMaster.tready) begin
				YcbcrMasterDriverVif.clockingBlockMaster.tdata<=req.tdata;
				YcbcrMasterDriverVif.clockingBlockMaster.Red[9:0] <= req.tdata[29:20];
				YcbcrMasterDriverVif.clockingBlockMaster.Blue[9:0] <= req.tdata[19:10];
				YcbcrMasterDriverVif.clockingBlockMaster.Green[9:0] <= req.tdata[9:0];
				repeat(req.tdataNumOfCyclesDelay) @(YcbcrMasterDriverVif.clockingBlockMaster);
			end
		end
		begin
			YcbcrMasterDriverVif.clockingBlockMaster.tlast<= (YcbcrMasterDriverVif.clockingBlockMaster.tvalid && 
                        YcbcrMasterDriverVif.clockingBlockMaster.tready) ? req.tlast : YcbcrMasterDriverVif.clockingBlockMaster.tlast;
			repeat(req.tlastNumOfCyclesDelay) @(YcbcrMasterDriverVif.clockingBlockMaster);
		end
	join
	`uvm_info(get_type_name(), $psprintf("driveSignals Finished"), UVM_DEBUG)
endtask

Thanks in advance for any answer.

In reply to nnn314:

Could you kindly add tags (SV one) to make it more readable. Adding indentations will help as well

In reply to Rsignori92:

Hey again, thanks for replying, you are absolutely right.

Fixed my code.

In reply to nnn314:

Thanks so much: so what I believe your TREADY signal is driven ? if so then you have your CB and the DUUT driving it. Just let me know first I need more hints about the logic. Regards

In reply to nnn314:

interface myif (input clk, input Reset);

    //Interface Signals
    logic my_sign;

    // Clocking block
    clocking cb_mst @(posedge clk);
        default input #1step output #1step;
        input my_sign;
    endclocking

    clocking sb_slv @(posedge clk);
        default input #1step output #1step;
        output my_sign;
    endclocking

    //Modports
    modport mon_port(input my_sign);
    modport mst_port(clocking cb_mst);
    modport slv_port(clocking sb_slv);
endinterface

This is just a piece of an highly simplified code. Please remove the clk and reset from MODPORT since those restriction in the access and no changing in the direction (they are always input).

In reply to Rsignori92:

In reply to nnn314:
Thanks so much: so what I believe your TREADY signal is driven ? if so then you have your CB and the DUUT driving it. Just let me know first I need more hints about the logic. Regards

Thanks for your answer!

You are correct, tready is being driven both by the dut and by the verification environment.

I changed my whole interface to wire instead of logic and it solved the issue.

In reply to Rsignori92:

In reply to nnn314:

interface myif (input clk, input Reset);
//Interface Signals
logic my_sign;
// Clocking block
clocking cb_mst @(posedge clk);
default input #1step output #1step;
input my_sign;
endclocking
clocking sb_slv @(posedge clk);
default input #1step output #1step;
output my_sign;
endclocking
//Modports
modport mon_port(input my_sign);
modport mst_port(clocking cb_mst);
modport slv_port(clocking sb_slv);
endinterface

This is just a piece of an highly simplified code. Please remove the clk and reset from MODPORT since those restriction in the access and no changing in the direction (they are always input).

The issue with removing clock and reset from modport is that the handle to the modport interface will not recognize the general interface’s inputs.
I tried removing it, the only option is changing the handle to point to the general interface.

In reply to nnn314:

why do you need to access the clk if you have clocking blocks there ?

In reply to Rsignori92:

Your questions triggered my thinking, thank you.

I do not need it, I changed it and it is working now.

In reply to nnn314:

ahahhahaha, no worries at all happy to help