Clocking block concept

SystemVerilog
1

interface dma_if(input logic clk,reset);

//---------------------------------------
//declaring the signals
//---------------------------------------
logic [31:0] addr;
logic wr_en;
logic valid;
logic [31:0] wdata;
logic [31:0] rdata;

//---------------------------------------
//driver clocking block
//---------------------------------------
clocking driver_cb @(posedge clk);
default input #1 output #1;
output addr;
output wr_en;
output valid;
output wdata;
input rdata;
endclocking

//---------------------------------------
//monitor clocking block
//---------------------------------------
clocking monitor_cb @(posedge clk);
default input #1 output #1;
input addr;
input wr_en;
input valid;
input wdata;
input rdata;
endclocking

//---------------------------------------
//driver modport
//---------------------------------------
modport DRIVER (clocking driver_cb,input clk,reset);

//---------------------------------------
//monitor modport
//---------------------------------------
modport MONITOR (clocking monitor_cb,input clk,reset);

endinterface

Hi, in the above interface code, in the driver clocking block what is the reason of taking input as rdata and output as wdata,addr, wr_en,valid and vice versa in monitor

2

In reply to mr.kry:

The signals addr,wr_en, valid, data are inputs the dut & driver will drive these signals to DUT and so these signals will become output from the driver, hence they are declared as output in driver clocking block.

In some cases driver needs to collect the rdata from the DUT, so rdata will become input the driver & hence it is declared as input in driver clocking block.

The monitor will sample all the output & input signals of DUT so all these signals will become inputs to the monitor and hence all the signals will be declared as inputs in monitor clocking block.

Note: Driver can drive & sample the DUT signals so that the driver clocking block can have both inputs and outputs. But monitor will always collect the DUT signals, it can not drive the signals and so in the monitor clocking block, all the signals will be inputs.

3

Thank you shanthi.