Clock sync assertions

SystemVerilog
,
1

hi ben

i am trying assertion to check clock synchronization
clk1=>200Mhz
clk2=>10mhz

both rising edges are triggers at same time in simulation but still my assertion is failing
property sync_clk;
@(posedge clk1)
($rose(clk1) && $rose(clk2));
endproperty

any issue with this assertion please let me know

2

In reply to abhiverif1715:

hi ben
i am trying assertion to check clock synchronization
clk1=>200Mhz
clk2=>10mhz
both rising edges are triggers at same time in simulation but still my assertion is failing
property sync_clk;
@(posedge clk1)
($rose(clk1) && $rose(clk2));
endproperty
any issue with this assertion please let me know

this is with mentor tool i could see both clocks rising edge in sync but assertion shwoing failure