Clock generator with intra delay or inter delay?

Could you clarify which of the following is better for clock generator

bit clk;
initial begin
   forever begin
      #5 clk=~clk;
   end
end
bit clk;
initial begin
   forever begin
       clk=#5~clk;
   end
end

form the simulation I am not seeing any difference .But is there any scenarios that makes one of the above is recommended.

I would avoid the second form as it requires an intermediate variable to store a temporary result. But I doubt you would see any performance difference unless all assignments in your design were like this.

BTW, please use code tags; I have added them for you this time.