Clock Generation Assertion

SystemVerilog
,
1

Hello All,

Please help me out with the assertion for checking the clk is generating or not wrt to ref_clk. if clock is not generating then assertion must be fired.
I tried this code by my self but it doesn’t work for all combinations.

module clk_stable;
  bit clk, ref_clk, RESET_N;
  
  property p();
    @(ref_clk) 
    1 |-> ##[0:5]($rose(clk)) ##[0:5]($fell(clk));
  endproperty
  
  a_1 : assert property(p)$display($time," Clk is Running");
    		else
              $display("Clk is stable at 1 or 0 state.");
    

    initial forever #200ns ref_clk = !ref_clk;
    initial forever #20ps clk = !clk;
    //initial forever #30ps clk = !clk;
    
    initial begin
    
      $dumpfile("dump.vcd"); $dumpvars;
 	  $display("START");
      repeat(30) @(posedge ref_clk); 
	  $finish; 
    end
 
    
    endmodule

if i keep this clk forever with 30 then it is working but when i keep the clk forever with 20 it gets negedge on posedge of ref clk and it fails.
Please help me out with it.

Thanks in advanced. :)

2

Your ref_clk should be small compared to the clk.(ie less than 20ps)
then its working properly.