Clock generation

SystemVerilog
1 
module abc;

bit clk;

assign #5 clk = ~clk;

endmodule

Is this way of generating clock valid? #5 here models inertial dealy, as the clock change duration and inertial delay exactly matches, will there be any issues?

2

In reply to yourcheers:

I recommend using a forever block for clock generation:


bit clk;

initial begin
  clk = 1'b0;
  forever #5 clk = ~clk;
end
3

In reply to cgales:

Thanks, I just wanted to understand disadvantages of continuous assignment in this context.

4

In reply to yourcheers:

The initial/forever form gives you better control of phase relationships when there are multiple clocks. You can do this by whether you set the first value of the clk to 0 or 1, and by putting a delay before the forever statement.