Let say I have three signal : input clk_in , input rst_b, output clk_out. How can I get an assertion to check if clk_out is toggling only after 2 clk_in cycles after the rising edge of rst_b. The assertion should fails if the clk_out is delayed more/less than 2 cycles and the assertion should also fail when clk_out stop toggle before rst_b goes 0. When rst_b ==0, the clk_out should be 0 too.
I have tried this:
property_assert: assert property(@(posedge clk_in or negedge clk_in) $rose(rst_b) |-> ((##[0:3] clk_out == 0) and (##4 (clk_out==clk_in) throughout rst_b)));
However, it still passing the following waveform: