Clock division in system verilog

Hi,

I have a DUT to which I am giving CLK1 as input and CLK2 is the output.

Whenever CLK1 changes then CLK2 becomes 5/6 times of CLK1 i.e. CLK2 = (5/6)*CLK1.

How can I approach this in system verilog to get CLK2 as 5/6 times of CLK1?

Thanks,
Shailendra

In reply to rajput7767:

In your case, time scale it vary important. Let’s say CLK1 half period is 1 ns, so CLK2 half period is 0.83333… ns. So you can chose time precision based on need.

In wave form CLK1 half period is 1000ps and CLK2 half period is 833ps.

For example, here i considered precision up to 1000 fraction of time unit.

`timescale 1ns/1ps

module top;
const int clk1_half_perido = 1;

bit clk1,clk2;
real clk2period;

initial
  forever begin
    #clk1_half_perido clk1 = ~clk1;
  end

initial
begin
  clk2period = (5.0/6)*clk1_half_perido;
  $display("clk1 period = %f", clk1_half_perido);
  $display("clk2 period = %f", clk2period);

end

initial begin
  @(posedge clk1);
  forever begin
    #clk2period clk2 = ~clk;
  end
end

initial
  #100  $finish;

endmodule // top

Thanks Prashant for this precise explanation.