Clock assertions

SystemVerilog
1

Hai team,

why do we get delay between the negedge and posedge of the clock?

I have written an assertion to check the freq of the clock. so at a point in between the clock my assertion is failing at T0ff. due to the delay between the negedge and the next posedge the time period is changed so that my assertions got failed.

any inputs on this how to overcome this?

2

In reply to Vickyvinayk:

Show the SVA code and testbench.
Ben

3

In reply to ben@SystemVerilog.us:

Hai ben… below is my assertion property to check the clock freq’s are expected. during clock generation (400Mhz clk), there is a gap between the clock. at one particular gap at negedge to posedge the Toff period is 116.25ns which is causing my assertions failure. the remaining clk TON and TOFF period is 1.25ns i:e 400MhZ expected.

property TON(clk,clk_period,duty_cycle,enable); 
      realtime first_change; 
     realtime period;
    realtime t_on_period=( ( clk_period * duty_cycle)/100 ); 
    disable iff(!reset ||!assert_event) 
     @(posedge clk)   
     (1,first_change=$realtime) ##0  
     @(negedge clk)  
     (1,period=($realtime-first_change)) ##0 
    //(period == t_on_period) ; 
    ((period <= (t_on_period + **1ns**)) && (period >= (t_on_period -**1ns** ))) ; 
  endproperty 

//Defining TOFF Property
   property TOFF(clk,clk_period,duty_cycle,enable); 
      realtime first_change; 
     realtime period; 
    realtime t_on_period=( ( clk_period * duty_cycle)/100 ); 
    realtime t_off_period =clk_period-t_on_period; 
    //disable iff(~assert_enable || reset || enable) 
    disable iff(~assert_enable || enable || rc2xtal_switch || rc2xtal_32k_switch||!assert_event) 
    //disable iff(!reset ||!assert_event) 
     @(negedge clk)   
     (1,first_change=$realtime) ##0  
     @(posedge clk)  
     (1,period=($realtime-first_change)) ##0 
    //(period == t_off_period) ; 
    ((period <= (t_off_period + **1ns**)) && (period >= (t_off_period - **1ns**))) ; 
  endproperty

Thanks for your response ben. One more question I need to ask is, actually the clk is generating 38.3995MHZ initially. After bootup it will generate the actual clk frequency of 400MHZ. So the issue here is when the clk is 38.3995Mhz due to small precision value the time period is not matching. so to avoid that I have added tolerance of 1ns but still the assertions are failing. is that the way to add the tolerance? please correct me if am wrong. And give me few inputs regarding how to handle the precision values and also for tolerance.

4

In reply to Vickyvinayk:

You might want to read timescale | Verification Academy

5

In reply to Vickyvinayk:

  • Handling timing tolerances The way you handling this looks ok.
    there is nothing magical about SVA; in fact it can be replaced with fork join_none constructs See my paper Understanding the SVA Engine,
    Verification Horizons - July 2020 | Verification Academy
    I wrote the following models last week using the fork join_any construct in an assertion. Edit code - EDA Playground I see an adaptation using this approach for your model; however, the use of SVA is OK. Also, I am not suggesting that you use the task method, but I am bringing this up to make the point we can tune the verification to the requirements.
  • Requirements Everything really boils down to requirements, and that includes tolerances, zones (or regions) for testing. Those zones or masks can be used as ANDing factors in the antecedents or disables of assertions. Examples of those zones are when the clk is initially at a frequency X then settles to frequency Y.
  • Precision values You can play around with the timeunit 1ns; timeprecision 100ps;

It all boils down to defining those envelopes when to check and for what to check.
SVA is just a language to help in the verification.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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