Class definition

SystemVerilog
,
1

Can we define class like below.

1.class OPCODE extends instruction; // OPCODE = ADD, SUB, MUL, FRC, etc
and after can we extend like below
2.class reg_range extends `OPCODE

I tried doing this but got the compilation error ?
please suggest me if i am missing something ?

2

In reply to rupeshblr:

Please see this post on how provide a good example for your question.