Class Declaration Issue

Hello all,

When compiling the code below, I get an error that says “System Verilog keyword ‘class’ is not expected to be used in this context” on the “class my_test extends uvm_test;” line. I can’t seem to find the issue it is having with this declaration, but I’m sure it must be something simple. Thanks in advance for any suggestions.

`ifndef ADDSUB_TB__SV
`define ADDSUB_TB__SV

`include "uvm_pkg.sv"
import uvm_pkg::*;

`include "8bitaddsub.sv"
`include "addsub_interface.sv"
`include "addsub_env.sv"

class my_test extends uvm_test;
	`uvm_component_utils(my_test)
	addsub_env addsub_env_h;
	
	function new(string name, uvm_component parent);
		super.new(name, parent);
	endfunction: new
	
	function void build_phase(uvm_phase phase);
		super.build_phase(phase);
		addsub_env_h= addsub_env::type_id::create("addsub_env_h", this);
	endfunction: build_phase
endclass: my_test
	
`endif

Usually a problem like this is because of an unfinished declaration that comes before it.

It would be much easier to find these kinds of problems if you did not include everything in to one big file and could separately compile things. Our recommendation is to put each class in a separate file, and include each class a package. Then you can compile each package independently. See an example of this here: UVC/UVMVerificationComponent | Verification Academy

Thank you for the response. I made the changes you suggested – all of my classes were already separated into different files, but I created a new file and included all of my files into that package, then imported the package into my top-level. I am now getting syntax errors in my module definitions, interface definitions, etc. Here is one situation as an example:

Error-[SE] Syntax error
Following verilog source has syntax error :
“addsub_interface.sv”, 10: token is ‘interface’
interface addsub_if(input clk);
^
System verilog keyword ‘interface’ is not expected to be used in this
context.

// My interface file
ifndef ADDSUB_INTERFACE__SV define ADDSUB_INTERFACE__SV
interface addsub_if(input clk);
//logic clk;
logic addsub, cin, cout;
logic [7:0] a, b, sum;
endinterface: addsub_if
`endif

// My package definition (for reference)
ifndef ADDSUB_PKG__SV define ADDSUB_PKG_SV
package addsub_pkg;
include "addsub_interface.sv" include “8bitaddsub.sv”
include "addsub_env.sv" include “8bitaddsub_tb.sv”
endpackage
`endif

Verilog modules and interfaces should be compiled as standalone files. They cannot be compiled into packages.

Packages are used to group classes, functions, tasks etc together. You `include class files in a package. You also import other packages which you reference in the package.

In reply to ValhallaOne:

Hi Dave,

code looks like;
/////////////////////////////////
class host_cfg extends uvm_object;

emulation emulation_1;
rand m_cfg m_cfg1;
rand n_reset_cfg n_reset_cfg_1;

endclass: host_cfg;
/////////////////////////////
Error;
variable type is not user defined type;
token is m_cfg1;
rand m_cfg m_cfg1;

issue with m_cfg1 or emulation_1 ?
where m_cfg is a package file.