Are class based SVAs possible? (Inside a monitor for example or even a scoreboard where is a semblance of clock).
Does system verilog allow this? If yes, is it a recommended practice?
Are class based SVAs possible? (Inside a monitor for example or even a scoreboard where is a semblance of clock).
Does system verilog allow this? If yes, is it a recommended practice?
In reply to kernalmode1:
No, you cannot use a clock-based concurrent assertion in a class. You scoreboard is supposed to be an abstraction above clock cycles. Put them in the interface that your monitor/driver communicates with.
In reply to dave_59:
See my paper on this topic
https://verificationacademy.com/forums/systemverilog/vf-horizonspaper-sva-alternative-complex-assertions
VF Horizons:PAPER: SVA Alternative for Complex Assertions
BEN SYSTEMVERILOG.US