why is class is not a stand-alone design unit whereas the module is a stand-alone unit
In reply to raja_zealster:
See the IEEE 1800-2017 SystemVerilog LRM operate on those data. A class’s data are referred to as class properties, and its subroutines are called methods; both are members of the class.
The class properties and methods, taken together, define the contents and capabilities of some kind of object.
You don’t simulate a type