Circular shift constraint

SystemVerilog
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1

Hi, I am trying to implement a constraint question, where if I do circular shift on input, it should not be equal to output. Please see the lnik below for my code.

Here, one of the outputs I am getting is “10000001”, which shouldn’t have been printed. Can someone please tell me the issue in this?

2

In reply to Akhil Mehta:

Tell us what you think you should be seeing. Or what is it you desire to see?

3

In reply to dave_59:

I should not see output like ‘10000001’ or ‘11000011’ or ‘01111110’

4

In reply to Akhil Mehta:


class rndm_gen;
  randc bit [7:0] value;
  constraint condition {value != {value[6:0],value[7]};}
endclass

module top;
  
  rndm_gen obj1=new;
  initial
    begin
      repeat(256)
        begin
          obj1.randomize();
          $display("%b",obj1.value);
        end
    end
  
endmodule

Run this code and analyze. I believe this one will satiate your requirement. In your code, when the value was getting a numerical figure at that time only it will check the constraint and if you observe at that moment for every case value2 is 0. Maybe this is the reason you were getting an undesired outcome.