Checking for time equivalence with sva assertion

SystemVerilog
,
1

Is it possible to check time equivalence with SV assertion? for example something like this:
assert property(@clk) ( x == 1 && y == 1) |=> (($time - previous_time) == (calculated_time))

Tx

2

See
https://verificationacademy.com/forums/systemverilog/checking-clock-period-using-system-verilog-assertion