Checking for signal toggle between defined time limit. Assertion or Functional Check?

Hello !

Prob: Have some analog signals for which I need to check for signal toggle. For Eg, If the signal toggles within a particular time limit [say 10ns], then condition passes and fails if the signal doesn’t toggle. Need to enable this check from the start of the process.

Was trying out using assertion, but unable to achieve the same. In general how to take care of such scenarios in assertions ? i.e. checking of signal toggles between some time intervals or so ??



property aloha;
  time cur_time;
  // @(posedge clk) (1,cur_time=$time) |-> ($stable(signal) throughout (($time-cur_time) == 10ns));
  @(signal) (1,cur_time=$time) |-> @(signal) ($time-cur_time <= 10ns);
endproperty: aloha
 
assert_aloha: assert property (aloha) begin $info("%m Worked %t\n", $time); end
              else begin $error("%m Failed\n"); end    


But was able to do a simple functional check to validate the same:



task launch_check();
  bit timeout = 0;
  forever begin
   fork
    begin
      @(signal);
    end 

    begin
      #10ns; timeout = 1;
    end
   join_any  
   disable fork; 
   if (timeout) begin $display("Error\n"); timeout = 0; end
  end
endtask: launch_check


Any inputs would be helpful !

In reply to desperadorocks:
SVA requires clocking events, but those events need not be clocks; they could be signals. Thus


    bit clk, a, b, clk1;   
    initial forever #10 clk=!clk;    
    property P;  // Option 1
        realtime t; // <----------- Use realtime 
        @(a) (1, t=$realtime) |=>  $realtime-t >= 9.99ns && $realtime-t <= 10.1ns; 
    endproperty 
    ap_P: assert property(P);  

    property P10; // Option 2
        realtime t; 
        @(a) (1, t=$realtime) |=>  $realtime-t == 10ns; 
    endproperty 
    ap_P10: assert property(P10);  

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy

In reply to ben@SystemVerilog.us:

Hello Ben,

But this assertion doesn’t get triggered/checked if the signal ‘a’ doesn’t change at all right ?
The check which I was trying to bring in is,
a. The signal should change within the required time i.e. 10ns from the start of the simulation.
b. If the signal doesn’t toggle then its an issue and the assertion should fail.

But the example which you posted above doesn’t get triggered if the signal doesn’t get toggled at all. How do we overcome that scenario ?

In reply to desperadorocks:

But this assertion doesn’t get triggered/checked if the signal ‘a’ doesn’t change at all right ?

Use the strong in the consequent


 property P10; 
        realtime t; 
        @(a) (1, t=$realtime) |=>  strong($realtime-t == 10ns); 
    endproperty

The check which I was trying to bring in is,
a. The signal should change within the required time i.e. 10ns from the start of the simulation.

In that case, the task approach is better. The assertion requires a clocking event

b. If the signal doesn’t toggle then its an issue and the assertion should fail.

The strong qualifier helps, but it still needs the signal to at least trigger

But the example which you posted above doesn’t get triggered if the signal doesn’t get toggled at all. How do we overcome that scenario ?

In that case, the task approach is better. The assertion requires a clocking event
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment