Checking for register state changes immediately after release of reset (removal violations)

SystemVerilog
, , ,
1

Some organizations (eg. ours) have a logic design requirement for reuse modules that no registers change state in the clock cycle or three immediately following removal of reset. The justification for this requirement is that it significantly reduces the potential design failure surface when exposed to improper reset implementation during integration.

I would like to test for this without adding too much boilerplate.

The possibilities I see are:

  1. Enumerate all state storage in the design at the top level (lots of boilerplate).
  2. Add inline assertions to every module (I have to modify the entire repository).
  3. Use a TCL script to iterate through the hierarchy of the design.
  4. Dump waveform and write a TCL script to parse it (adds an additional tool to the verification flow).

I’m hoping there is some SystemVerilog mechanism that I don’t know about that does something like return the flattened state of a module. Then I can do something like this:

rstn = 0;
preResetState = func_hash( $state(dut) ) + func_hash( $state(dut.inner ) ) + ...
rstn = 1;
@(posedge clk);
postResetState = func_hash( $state(dut) ) + func_hash( $state(dut.inner) ) + ...
assert( preResetState  == postResetState  );

How is this normally tested?

DP

2

In reply to dave_79:

Hi Dave,


  //Option:1
  property p_reset_removal_check(reset, register_data);
    int prev_reg_val;
    @(posedge Clock) 
          ($rise(reset), prev_reg_val=register_data) |=> (prev_reg_val == register_data);
  endproperty

  //Option:2
  property p_reset_removal_check;
    @(posedge Clock) 
          $rise(reset) |=> ( register_data ==  $past(register_data));
  endproperty


Hope this will help you...