Checking if two signals became 0->1 at same time

hi i want to know if there is a way in sv by which we can find if two signals became 1 at same time or 2nd siganl became 1 1clock before first signal or 1 clock after first signal.

i have a requirment to see if two signal in my RTL ever became 1 at same time.

In reply to pawan:

cover property (@(posdege clock) $rose(sig1) && $rose(sig2));

cover property (@(posdege clock) $rose(sig1) && $rose(sig2)); //sig1 and sig2 assert at same time
cover property (@(posedge clock) $rose(sig1) ##1 $rose(sig2)); //sig1 assert 1 clock before sig2 assert
cover property (@(posedge clock) $rose(sig2) ##1 $rose(sig1)); //sig2 assert 1 clock before sig1
assert