Checking clock toggle after ack signal is high

SystemVerilog
1

Need to check a clock toggling/period continuously till the end of simulation when ack is high.
ack is asserted first, then the clock.

Using property(@posedge clock) will not work, since i want ack to be asserted first. Any suggestions?

2

In reply to abhi9891:
Below is an untested solution. Need to adjust the values for the period, I made it 2x the number of edges.


   realtime period=20ns;
    bit ack;
    initial begin
      bit got_edge;
      wait(ack);
      forever begin : fv1
        fork
          begin #period; end
            begin 
              @(posedge clk) got_edge=1'b1; 
            end    
        join_any
        a_gotclk: assert(got_edge); 
        got_edge=0; 
      end : fv1
    end

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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