Checking 60% duty cycle clock

Question

I am asserting to check whether the clock is meeting 60% duty cycle using following code (The code is working for my intention)

`define PERIOD 10ns
 
module tb;
 
    realtime TON = `PERIOD * 0.6;
    realtime TOFF = `PERIOD * 0.4;
 
    int clock;
 
    initial begin
        clock = 1;
    end
    always begin
        #6 clock = 0;
        #4 clock = 1;
    end 
 
    property check_ton(int ton_time);
        time current_time;
        (1, current_time = $realtime) |=> @(negedge clock) (ton_time == ($realtime-current_time));
    endproperty : check_ton
 
    property check_toff(int toff_time);
        time current_time;
        (1, current_time = $realtime) |=> @(posedge clock) (toff_time == ($realtime-current_time));
    endproperty : check_toff
 
    assert property ( @(posedge clock) check_ton(TON))
        $display($time," CHECK_TON : PASS");
    else $warning($time," CHECK_TON : FAIL");
 
    assert property ( @(negedge clock) check_toff(TOFF))
        $display($time," CHECK_TOFF : PASS\n");
    else $warning($time," CHECK_TOFF : FAIL\n");
 
    initial begin
        #50 $finish;
    end
endmodule :tb

There are 2 assertions: check_ton and check_toff.
I want to combine them into one assertion.
How should I write the code.

Answer 1

Solution

ben@SystemVerilog.us

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2038 posts

February 24, 2021 at 3:04 am

In reply to bachan21:

There is no reason to combine them into a single assertion.
The general recommendation is to write smaller simple assertions rather than complex fewer ones.

BTW, use realtime instead of time.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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Answer 2

bachan21

Forum Access

61 posts

February 24, 2021 at 3:23 am

In reply to ben@SystemVerilog.us:

Thanks for the guidelines Ben

Answer 3

Arshia

Full Access

4 posts

March 12, 2021 at 4:37 am

In reply to bachan21:

Hello Bachan,

Can u please explain how to generate the clock with 25MHZ frequency with 50% duty cycle without assertions.

Thanks in Advance,
Arshia J

Answer 4

ben@SystemVerilog.us

Full Access

2038 posts

March 12, 2021 at 9:05 am

In reply to Arshia:

You do not generate clocks with assertions. Bachan verified the clock periods with assertions.
The clock was generated with SV code using the always construct.

What gave the impression that assertions generate clocks. That is definitely no their purpose.
Ben

Answer 5

bachan21

Forum Access

61 posts

March 15, 2021 at 11:52 pm

In reply to Arshia:

Hi Arshia,
As Ben explained, we cant use assertion for generating clock. In this problem, I used assertions to verify my clock.

If you want to generate 25 MHz clock, follow the below instructions.

Quote:

Convert 25MHz into time period terms.
25 MHz -> 40 ns in time period
As the duty cycle is 50%, the clock changes its value every 20 ns

Use the below code for 25 MHz clock

`timescale 1ns/1ps
module tb;
  bit clock;
 
  always 
    #20 clock = !clock;
endmodule

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