What is the difference between assertion and checkers?
Can we say that an immediat assertion is a checker?
In reply to kartik@23Patel:
See 1800’2017 section 17 Checkers
Also see 1800’2017 **16.3 Immediate assertions
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In reply to kartik@23Patel:
You have to sometimes distinguish between SystemVerilog keywords and general industry terminology. From a keyword perspective, SystemVerilog has a hierarchy of constructs that start from Boolean expressions, to sequences and properties, and on to assertions and checkers.
From an english language perspective, sometimes these words get used interchangeably to mean a section of code used to verify correct behavior. Broadly that means your entire testbench could be considered a “checker”.