Checker for clock frequnce

SystemVerilog
, ,
1

I have a module which running in specif two frequency.
I wan to develope assertions for checking two freq simultaneously. But ()either of them will exist in one simulation randomly.

Can anyone pls suggest some approch of doing same?

2 
module test9;
  // I have a module that runs in specifically two frequencies.
  // I wan to develop assertions for checking two freq simultaneously. 
  // But ()either of them will exist in one simulation randomly.
  parameter time P1=20ns; // half period 
  parameter time P2=35;   // half period 
  bit clk1, clk2, f1_select, f2_select; 
  property p_f1_check;
  		time v_t; 
  	    @(posedge clk1) (f1_select, v_t=$time) |-> @(negedge clk1) $time-v_t==P1;
  endproperty 
  ap_f1: assert property(p_f1_check); 
  
   property p_f2_check;
  		time v_t; 
  	    @(posedge clk2) (f2_select, v_t=$time) |-> @(negedge clk2) $time-v_t==P2;
  endproperty 
  ap_f2: assert property(p_f2_check); 
  
  // If you need an activity detector for the frequency that is not running, you'll need to 
  // do that is code. An alternate solution is to create a test clock to check that at 
  // those edges, the inactive clock is indeed stable, or at the 0 level (if that is the case). 
  
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115