Checker

write a checker code
i have two signals clk and reset are sending to dut at every posedge clk i need to get reset signal but reset signal will not get back to back it means at first clock cycle and at 3d cycle and 5th cycle i need to get reset write code for that without using assertions

In reply to VARIKELA RAKESH:

Sorry to tell you that but your requirements are totally unclear.
“need to get” what does that mean?
2 signals, one toggles every other clock. Now what? Design? Verify?
Totally ambitious.

In reply to ben@SystemVerilog.us:
you need to write the code for that means reset will get high at every posedge of clk but not back to back reset signal

In reply to VARIKELA RAKESH:

See my hand written note.
Google Photos
If I totally misunderstood your question, which I probably did since it still isn’t clear, you need to draw a timing diagram first.
The logic flows easily from there.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: