Check is a signal is stable for the past 'n' clock cycles

SystemVerilog
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1

I have two signals “a” and “b”. The relationship between these two signals is that “b” will be asserted if “a” was stable(and 0) for the past “n” clock cycles. The time “n” here is a variable time.

How can I write an assertion which checks for the following:
If “b” is asserted, “a” must have been stable(and 0) for the past “n” clock cycles

Here is what I have written to check this:


   property stability_for_past_n_clks (clk,a,b,n);
   int t;
   disable iff (ares)
   @(posedge clk)
     ($rose(b),t=n+1'b1) |-> ($past($stable(!a),t),t=t-1'b1)[*0:$] ##1 t==0 ;
   endproperty

Will this work?

Thanks,
Rajesh

2

In reply to chitturi:

Hello.
You could noticeably simplify your property through the use of auxiliary logic.
For example:


integer counter;
always @(posedge clk or negedge rst_n)
  if(!rst_n || a) begin
     counter = 0;
  end else if(counter < n) begin
     counter++;
  end

property stability_for_past_n_clks();
  disable iff (!rst_n)
  @(posedge clk) $rose(b) |-> (counter == n);
endproperty

Best regards, Maksim.