In reply to peter:
There are some caveats in using functions as an expression:
- If the function has a return then you can use it
function int B(bit m, n); return m && n; endfunction
ap_p1: assert property(@(posedge clk) $rose(a) |-> B(x,y) ##1 c); // OK
ap_p2: assert property(@(posedge clk) $rose(a) |-> d==B(x,y) ##1 c); // OK
- Function with return type of void cannot be used in/as an expression.
- tasks cannot be used as an expression.
- Void functions and tasks can be used in a sequence_match_item
- You should avoid using tasks in an assertion, particularly if the task is time consuming
function void inc_sop(bit c);
sop_count=sop_count+1;
endfunction: inc_sop
// ERROR: Function with return type of void cannot be used in/as an expression.
ap_ERROR: assert property(1 |-> inc_sop(sop));
// OK
ap_OK: assert property(1 |-> (1, inc_sop(sop)) );
task automatic inc2_sop(bit c);
sop_count=sop_count+1;
endtask: inc2_sop
ap_OK2: assert property(w |-> (e,inc_sop(sop)));
Ben Cohen
http://www.systemverilog.us/
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats
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2) Free books:
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Understanding the SVA Engine,
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Reflections on Users’ Experiences with SVA, part 1
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Reflections on Users’ Experiences with SVA, part 2
https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-experiences-with-sva-part-2
SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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