Check that output changes on negedge of clk - sva

[AnaMariaRadu]

Hi,

Im trying to write an assertion in which I want to verify that an output, for instance, data_read, changes on a negedge of clk. Sounds simple, but Ive tried a lot of “solutions” but with no success. Maybe I am stuck in a wrong way of thinking the assertion.
Thank you for help!

Ana.

[ben2]

In reply to AnaMariaRadu:

Im trying to write an assertion in which I want to verify that an output, for instance, data_read, changes on a negedge of clk. Sounds simple, but Ive tried a lot of “solutions” but with no success. Maybe I am stuck in a wrong way of thinking the assertion.

I would consider 1800’2012:: 31.8 Vector signals in timing checks with the $setup, $hold
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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