Check multi asynchronous signal

SystemVerilog
1

there’s some asynchronous signal, a, b, c, and clk (not for a,b,c)

  1. at initial time, all these signals is 0 or 1, and clk is not toggling. (not need check)
  2. then control flow start, start of work, and clk start to toggle. (not need check)
  3. at some time, a, b, c should be 1, and clk keep toggling (need to check here!)
  4. and control flow continues. (not need check)
  5. at some time, stop of work, a, b, c should be 0, and clk stop toggling (need to check here!)
  6. and control flow continues, re-start of work . (not need check)
  7. at some time, a, b, c should be 1, and clk keep toggling (need to check here!)

so I need check in step 3, 5, 7, and the difficult is I cannot know time point, can I check this in efficient way？
or I should breakdown control flow like this, a=0->b=0,b=0->c=0,c=0->clk stop togging…

very appreciated if you can give some tips here.

2

In reply to guorke:

There is a lot of missing information here.

I assume “control flow” is an enabling signal.

For step 3, When you say “at some time, a, b, c should be 1” do you mean simultaneous, or independently? That could be
wait(a&&b&&c) or
fork wait(a); wait(b); wait(c); join.

Do you have a reference clock to compare your actual clk to? If yes, then you can create counters for each clock and make sure the counters match. If no, there really is no way to know that a clock keeps toggling unless you have some time period to know how often it should toggle.

Same question for step 5, simultaneous or independent?

And is step 6 just a loop back to step 3?

And what happens if there is a failure in any of these steps? Do you stop checking, or is there some recovery process waiting for the control flow start?

3

In reply to dave_59:

In reply to dave_59:

thanks Dave, like this
signal step1 step2 step3 step4 step5
clk 0 0 toggle toggle 0
a 0 1 1 0 0
b 1 1 1 1 0
c 0 1 1 0 0
there’s relation between a,b and c, which’s defined control flow, but we don’t need check there.

a,b,c should be 1, not need same time, but from result view, there’s a time slot all three signal should be 1 ,and clock toggling.

no reference clock, but we may can use @(posedge clk) @(negedge clk); no need to be very accurate for this.

step5. same as above.
step6, yes, same as step3.

if all these check failure, just print UVM_ERROR message. not need any other operation.