In reply to Ankit Bhange:
A small variation to my model, plus an SVA assertion. Adjust the time when a==1.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, a;
event e, e0, e1;
initial begin
#39;
forever #5 clk=!clk;
end
/* When clock starts running, signal A should be low for at least 1us.*/
let T=1000ns; // at 10ns/cycle then 100 clocks
task automatic t_count();
int count;
fork
fork1: begin
-> e0;
forever begin
@(posedge clk) count += 1'b1;
end
//disable fork2;
end
/* fork2: begin
#T;
disable fork1;
-> e1;
end */
fork3: begin
@(posedge a); // "a" signal is asserted.
disable fork1;
// disable fork2;
end
join_any
$display("%t count= %d ", $realtime, count);
a_t_count: assert (count >= 100) else -> e; // error
endtask
initial begin
a_aIS0: assert(a==1'b0); // "a" starts at 0
t_count();
end
property p_100before_a;
int v_count=0;
@(posedge clk) first_match((a==1'b0, v_count+=1'b1) [*1:$] ##1 $rose(a))
##0 v_count >=100;
endproperty
initial ap_100before_a: assert property(@ (posedge clk) p_100before_a );
initial begin
#1399 a <= 1'b1;
end
endmodule
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact
http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats
https://rb.gy/a89jlh
2) Free books: Component Design by Example
https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3)
https://rb.gy/cwy7nb
3) Papers:
- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
