In reply to pagarwa5:
The [->1] is the goto operator.
goto repetition, Boolean ([->n], [|->n:m])
Rule: The goto repetition operator (Boolean[->n]) allows a Boolean expression (and not a sequence) to be repeated in either consecutive or non-consecutive cycles, but the Boolean expression must hold on the last cycle of the expression being repeated. The number of repetitions can be a fixed constant or a fixed range.
Note: b [->m] is equivalent to ( !b [*0:$] ##1 b)[*m]
thus,
b[->1] is equivalent to: !b[*0:$] ##1 b
b[->2] is equivalent to: !b[*0:$] ##1 b ##1 !b[*0:$] ##1 b
// You could have written the following
$rose(state==A) ##1 done[->1] |=> (state==B, $display(" A - B")) ;
// as
first_match($rose(state==A) ##[1:$] done[->1]) |=> (state==B, $display(" A - B")) ;
The first_match() is needed because SVA requires that each of the threads of a multithreaded antecedent be tested with its appropriate consequent.
With the goto, the cycle done==1'b1 guarantees that there could not be other threads with
!done ##1 done.
The general recommendation by experts in SVA is to avoid the first_match() if you can because it is more stylish and readable. I interpret a[->1} as the "first occurrence of "a".
On a separate note, I strongly suggest that take a look at my package for dynamic delays and repeats. Even if you don't use it right now, study the code, you'll learn a few things.
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact http://cvcblr.com/home
* SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
* Component Design by Example ", 2001 ISBN 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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1) SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
2) https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
3) SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment