Changing clock frequency during simulation run

Hi,

how to change the same clock frequency during the simulation in the TB.

let say i run the simulation for 2000ns so for 500ns clock frequency should be 200mhz then next 500ns same clock frequency should be 100mhz then next 500ns 300mhz like so on.

Any leads ?

In reply to rkg_:

Create a clock agent with a driver that generates a clock signal with a variable delay. When you want to change the clock frequency, send a sequence item with the new delay.

In reply to cgales:

Thanks for reply !!

Any alternative method in SV or Verilog to generate the same ? if I don’t want to use UVM stuff here.

In reply to rkg_:

Use an interface that generates a clock signal with a variable delay. When you want to change the clock frequency, call a function in the interface with the new delay,

In reply to cgales:

Hi,

Could you please provide me pseudo code ?

In reply to rkg_:


`timescale 1ps/1ps
interface clk_gen(clk);
  output bit clk;
  
  shortint half_cycle = 1000;
  
  initial begin
    clk = 0;
    forever #half_cycle clk = ~clk;
  end
  
  function void set_half_cycle(shortint c);
    if (half_cycle == 0) begin
      $display("Error - can't set clock half_cycle to 0");
    end
    else begin
      half_cycle = c;
    end
  endfunction
endinterface

module testbench();
  wire clk;
  
  clk_gen clk_gen0(clk);
  
  initial begin
    repeat (100) @(posedge clk);
    clk_gen0.set_half_cycle(500);
    repeat (100) @(posedge clk);
    clk_gen0.set_half_cycle(20);
    repeat (100) @(posedge clk);
    clk_gen0.set_half_cycle(200);
    repeat (100) @(posedge clk);
    $finish;
  end
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1);
  end
endmodule

In reply to cgales:

Thanks for reply .