For case structure

SystemVerilog
1

I have this piece of code which gives me priority decoder when I do synthesis. Is there any easy way we can avoid priorirty decoder and use the for loop or is there any generic case statement which we can write without knowing the number of case match expressions before head?

 1 for( int ii = 0; ii < MAX_REGISTERS; ii++ ) begin : register_loop
  2   if( valid && ii == addr[ADDR_WIDTH-1:0] ) begin
  3     if( cmd ) begin
  4        data <= register[ii];
  5     end
  6   end
  7 end