Cannot evaluate the expression in left slicing expression

SystemVerilog
,
1 

j=(7*i)+i;
k=j+7;
slv_mem[drv_if.a_address][k:j]  = drv_if.a_data[k:j];

In this code I’m getting 2 errors.
ERROR-1 : The range of the part select is illegal.
Unknown range in part select.this.drv_if.a_data[k:j]
ERROR-2 : “k”
Cannot evaluate the expression in left slicing expression.
The expression must be compile time constant.

2

In reply to K.Abhishek:


j=(7*i)+i;
slv_mem[drv_if.a_address][k+:7] = drv_if.a_data[k+:7];