Can you use a radix to print readable names in Verilog (or SystemVerilog)?

SystemVerilog
, ,
1

When working with the Modelsim GUI (and Quartus SignalTap), I define readable names using a radix like this:

radix define CMD_RAM {
     "3'b000" "LOAD REG"   -color "Yellow",
     "3'b001" "REFRESH"    -color "Yellow",
     "3'b010" "PRECHARGE"  -color "Yellow",
     "3'b011" "ACTIVE"     -color "Yellow",
     "3'b100" "WRITE"      -color "Yellow",
     "3'b101" "READ"       -color "Yellow",
     "3'b110" "BURST TERM" -color "Yellow",
     "3'b111" "NOP"        -color "Yellow",
     -default default
 }

Is there a way of printing values using $display or $strobe which will also use a similar radix definiton?

2

In reply to SparkyNZ:

I recommend using an enumeration in your code. You can then use the .name() function to print the value of the variable:


module test();
  typedef enum bit [2:0] {
    LOAD_REG, REFRESH, PRECHARGE, ACTIVE, WRITE, READ, BURST_TERM, NOP
  } CMD_RAM_t;

  CMD_RAM_t cmd;

  initial begin
    cmd = REFRESH;
    $display("Command is %s", cmd.name());
    cmd = WRITE;
    $display("Command is %s", cmd.name());
    cmd = BURST_TERM;
    $display("Command is %s", cmd.name());
  end
endmodule

You could also create an associative array as shown here, but it isn’t as efficient.

3

In reply to cgales:

Perfect. Thanks!