I am working with host- device architecture and want to build a connection between that two modules . My question is that is it possible to use 2 different instances and connect 1’s txdata line to 2nd’s rxdata line in top module ?
In reply to meeteedesai:
interface my_if;
bit [ 7 : 0 ] txdata;
bit [ 7 : 0 ] rxdata;
endinterface
module top;
my_if foo();
my_if bar();
assign foo.txdata = bar.rxdata;
endmodule
You’re probably looking for something else, but this matches your stated requirements.
Regards,
Mark
In reply to meeteedesai:
SystemVerilog does not make it easy to connect different interface instances together. You have to connect each signal individually. The simplest approach is putting the signals you want to connect in the port list of the interface
interface channel(inout txdata, rxdata);
wire data;
endinterface
module host(channel p);
// drive p.txdata
// read p.rxdata
endmodule
module device(channel p);
// drive p.txdata
// read p.rxdata
endmodule
module top;
wire line1, line2;
channel h(.txdata(line1), .rxdata(line2));
channel d(.rxdata(line1), .txdata(line2));
host u1(h);
device u2(d);
endmodule
Another option is using a single interface with modport expressions
interface channel;
logic line1,line2;
wire data;
modport h(output .txdata(line1), input .rxdata(line2));
modport d(input .rxdata(line1), output .txdata(line2));
endinterface
module host(channel.h p);
// drive p.txdata
// read p.rxdata
endmodule
module device(channel.d p);
// drive p.txdata
// read p.rxdata
endmodule
module top;
channel c();
host u1(c);
device u2(c);
endmodule
In reply to dave_59:
-
I am aware about the signal to signal connection in interface but what-if I change the configuration and replace the device with hub ? In that case I have to change all the port signals right? What would be suitable approach in that case ?
-
In 2nd approach I have other signals as well which deals with their respective host/device DUTs, Wouldn’t be an issue if I just have a single instance of interface with different modports in that situation ?