typedef enum{MEM_WR,MEM_RD,IO_WR,IO_RD,CFG_WR,CFG_RD}packet_type;
class packet;
rand packet_type pkt_type;
rand bit [31:0] addr;
rand longint [9:0] length;
rand bit [31:0] data[];
rand bit[7:0] tag[];
constraint word_aligned{
addr[2:0] == 3'b0;
}
constraint max_length{
data.size() == length;
}
constraint addr_c{
(pkt_type == MEM_WR || MEM_RD) -> (addr > 'h4FFF);
(pkt_type == IO_WR || IO_RD) -> (addr inside { [ 'h4000 : 'h4FFF ] });
(pkt_type == CFG_WR || CFG_RD) -> (addr inside { [ 'h0 : 'h3FFF ] });
}
constraint length_c{
(pkt_type == MEM_WR || MEM_RD) -> (length inside { [1:1023] });
(pkt_type == CFG_WR || CFG_RD || IO_WR || IO_RD ) -> (length == 1);
}
constraint weight_c{
pkt_type dist { (MEM_WR && MEM_RD):= 50, (CFG_WR && CFG_RD):= 30,
(IO_WR && IO_RD):= 20 };
}
constraint tag_val{ foreach(tag[i]) { tag[i] =i; if(tag[i] > 127) -> tag[i] = tag[i-1]-1 ;}
} endclass
The above code is with respect to the following problem
Create a packet class with the following,
Address - 32 bit double world aligned(32 bit aligned)
Length - 10 bit , Number of double words(32 bit) in data
Data - A collection of 32 bit data, number of items as specified by length.
type - Mem WR, Mem RD, IO WR, IO RD, CFG WR, CFG RD
Tag - values from 0 to 127
Rules
- Address is always 32 bit aligned. Address should be from 0 to 3FFF for CFG types and 4000 to 4FFF for IO types. Above that is always memory types
- Length is always 1 for CFG and IO types and can be 1-1023 or Mem types
- Weightage of packet type should be as below
MEM - 50%
CFG - 30%
I/O - 20% - Tag should be linearly incrementing for different packets. Ie 0,1,2…127 only after 127 it should go back to 0 and re start from there.
- Make sure that there is no repetition in data elements.