Can we reference a struct element which is two level down the hierarchy?

SystemVerilog
1

Hi,

I have one query regarding system verilog structures.

Please refer the example below.

class packet; 
        typedef struct {
             logic  reg_1 = {0,0,0,0,0,0,1,0,0,0,0,0,0,1,0,0,0,1,1,1,1,1,1,1,1,0,0,0,1,1,0,0};
             logic  reg_2 = {0,0,0,0,0,0,1,1,1,1,1,1,0,1,0,0,0,1,1,1,1,1,1,1,1,0,0,0,1,1,0,0};
        } register_set; 
 
        register_set reg_name; 
 
endclass: packet

With the above structure… we can access the elements as shown below.
reg_name.reg_1 = 32’h____;
reg_name.reg_2 = 32’h____;

My query is,
Is it possible to define a structure exactly the way registers are being modeled?
If reg_1 has fields ctrl1, ctrl2, ctrl3 and ctrl4 in the RAL.

reg_1 = (… [31:25] ctrl4,
[23:16] ctrl3,
[15:8] ctrl2,
[7:0] ctrl3,
…)

I am not following the exact ral synatx here… This is just for showing the intent.

I would like add these fields under reg_1 inside the structure and then I would like accesses the elements via struct handle…
something like this…
reg_name.reg_1.ctrl4

Is there a way… Could someone help me with this…

2

I guess you could just make a structure reg with 4 8-bit members ctrl1 - ctrl4 and then make a structure of those, like this:


typedef struct {
logic [7:0] ctrl1;
logic [7:0] ctrl2;
logic [7:0] ctrl3;
logic [7:0] ctrl4;
} register;

typedef struct {
register reg1;
register reg2;
} register_set;