Can we instantiate a cover group within a class?

SystemVerilog
1

Hi,

I’m stuck in a problem. I need to know if we can instantiate a covergroup more than once within a class?

The summarized version of my code is presented below…

class A extends B;

 bit [5:0] var1;
 bit [5:0] var2;

 function declare();
     var1 = 6'd35;
     var2 = 6'd23;
 endfunction

 covergroup cg();
     point: coverpoint var1{
           bins bin1 = {22};
           bins bin2 = {12};
           }
 endgroup

 // variable 2 has same coverpoints as variable1 and 1 want it to be declared here     //somewhow

 virtual task run();
 begin
     declare();
     cg.sample();
 end
 endtask

endclass

this is an intermediate coverage model which is being run using a make file.

Please help me out with this.

Thank you

2

No you can’t. You need to declare the covergroup outside the class and declare a covergroup argument so that you can pass var1 and var2 to it.

3

In reply to dave_59:

You can declare a covergroup inside a class (I think this is called “embedded”), but only one instance of it is allowed within the class. But to do what you want, you can put your covergroup with declared argument inside a separate “wrapper” class, whose constructor can pass var1 or var2 to it as Dave indicated. Then you can make as many instances (objects) of the wrapper class as you want (inside your other class).

4

In reply to edcarstens:

I have few queries…
i have copied a code from one of the examples given in the class and trying to modify it little bit.
a DUT is basically a calculator having four ports add subtract shift right and left and no operation of 4 bit long.
there is an error that says “illegal non array type for set expression in bin ‘null_ops’ of coverpoint all_ops”… then i removed this particular allops and then it thrwos an error
undefined variable OC but i did create an object OC
op_cov oc;

i want to know how can i include this covergroup in the testbench module. if not what is the other feasible way.(considering i do not have a great knowledge of SV)

the code goes this way…

covergroup op_cov;
 
coverpoint op_set {
 
 
bins single_cycle[] = {[add_op : shift_Rop],rst_op,no_op};
bins multi_cycle[] = {[add_op : shift_Rop],rst_op,no_op};
 
 
bins opn_rst[] = ([add_op : shift_Rop] => rst_op);
bins rst_opn[] = (rst_op =>[add_op : shift_Rop]);
 
 
bins sngl_rshft[] = ([add_op:shift_Lop], no_op => shift_Rop);
bins rshft_sngl[] = (shift_Rop => [add_op:shift_Lop], no_op);
 
 
bins sngl_lshft[] = ([add_op:sub_op],shift_Rop, no_op => shift_Lop);
bins lshft_sngl[] = (shift_Lop => [add_op:sub_op],shift_Rop, no_op);
 
}
endgroup
 
covergroup zeros_or_ones_on_ops;
 
all_ops : coverpoint op_set{
ignore_bins null_ops = no_op ; }
 
req1_data_in_leg : coverpoint req1_data_in {
bins zeros = {'h00000000};
bins others = {['h00000001 : 'hFFFFFFFE]};
bins ones = {'hFFFF};
}
 
req2_data_in_leg : coverpoint req2_data_in {
bins zeros = {'h00000000};
bins others = {['h00000001 : 'hFFFFFFFE]};
bins ones = {'hFFFF};
}
 
 
req3_data_in_leg : coverpoint req3_data_in {
bins zeros = {'h00000000};
bins others = {['h00000001 : 'hFFFFFFFE]};
bins ones = {'hFFFF};
}
 
 
req4_data_in_leg : coverpoint req4_data_in {
bins zeros = {'h00000000};
bins others = {['h00000001 : 'hFFFFFFFE]};
bins ones = {'hFFFF};
}
 
op_00_FF: cross req1_data_in_leg, req2_data_in_leg, req3_data_in_leg, req4_data_in_leg, all_ops{
bins add_00 = binsof (all_ops) intersect {add_op} &&
              (binsof (req1_data_in_leg.zeros) || binsof (req2_data_in_leg.zeros) || binsof (req3_data_in_leg.zeros) || binsof (req4_data_in_leg.zeros));
 
bins add_FF = binsof (all_ops) intersect {add_op} &&
              (binsof (req1_data_in_leg.ones) || binsof (req2_data_in_leg.ones) || binsof (req3_data_in_leg.ones) || binsof (req4_data_in_leg.ones));
 
 
 
bins sub_00 = binsof (all_ops) intersect {sub_op} &&
              (binsof (req1_data_in_leg.zeros) || binsof (req2_data_in_leg.zeros) || binsof (req3_data_in_leg.zeros) || binsof (req4_data_in_leg.zeros));
 
bins sub_FF = binsof (all_ops) intersect {sub_op} &&
              (binsof (req1_data_in_leg.ones) || binsof (req2_data_in_leg.ones) || binsof (req3_data_in_leg.ones) || binsof (req4_data_in_leg.ones));
 
 
 
bins shftl_00 = binsof (all_ops) intersect {shift_Lop} &&
              (binsof (req1_data_in_leg.zeros) || binsof (req2_data_in_leg.zeros) || binsof (req3_data_in_leg.zeros) || binsof (req4_data_in_leg.zeros));
 
bins shftl_FF = binsof (all_ops) intersect {shift_Lop} &&
              (binsof (req1_data_in_leg.ones) || binsof (req2_data_in_leg.ones) || binsof (req3_data_in_leg.ones) || binsof (req4_data_in_leg.ones));
 
 
 
 
bins shftr_00 = binsof (all_ops) intersect {shift_Rop} &&
              (binsof (req1_data_in_leg.zeros) || binsof (req2_data_in_leg.zeros) || binsof (req3_data_in_leg.zeros) || binsof (req4_data_in_leg.zeros));
 
bins shftr_FF = binsof (all_ops) intersect {shift_Rop} &&
              (binsof (req1_data_in_leg.ones) || binsof (req2_data_in_leg.ones) || binsof (req3_data_in_leg.ones) || binsof (req4_data_in_leg.ones));
 
ignore_bins others_only =
              binsof (req1_data_in_leg.others) && binsof (req2_data_in_leg.others) && binsof (req3_data_in_leg.others) && binsof (req4_data_in_leg.others);
 
}
 
endgroup
 
module coverage
op_cov oc;
zeros_or_ones_on_ops c_00_FF;
 
typedef enum bit [3:0] {
 
}
 
 **
initial begin : coverage
 
oc = new();
c_00_FF = new();
 
forever begin @(negedge clk)
oc.sample ();
c_00_FF.sample ();
end**
 
end : coverage

can someone help

5

In reply to dave_59:

Hai dave.

can you give an example of that?

actually, I have written the cover group inside the class it is something like

class monitor_class extends uvm_monitor;

function new();
cg=new(); // but here i am getting an compilation error as undeclared identifier.
endfunction

virtual task run_phase(uvm_phase phase);
cg.sample();
endtask
covergroup cg;
// written few coverpoints here
endgroup
endclass