Can we initialize a member of class as below

SystemVerilog
,
1

Hi All,

Can we initialize a member of class by passing a value in new function as below.
I could access with object but i want to see variable a can be initialized as in code

program main;
  class baseclass;
    int a;

    task display;
      $display("a=%d",a);
    endtask:display
  endclass:baseclass

  initial begin
    baseclass b;
    b=new(10);
    //b.a=10;
    b.display();
  end
endprogram:main

Thanks
Bharathece

2

You could, if your class declaration looked like


class baseclass;
    int a;
    function new(int _a);
       a = _a;
    endfunction 
    task display;
      $display("a=%d",a);
    endtask:display
endclass:baseclass

However, I would not recommend doing it this way as this creates a number a problems later on. If you start adding more arguments to the constructor, you have to change your code everywhere the class is constructed. The UVM factory does not allow this anyways.

3

Thanks Dave…What do you mean is that Actual arguments should be matching formal arguments.

What UVM factory does not allow(with curiosity iam asking).Is that this way initializing the members of a class?

Thanks
Bharath

4

In reply to bharath123:

As with any function or task, if you start changing the formal arguments of a routine, then you either need to provide proper defaults, or you must change the actual arguments everywhere the routine is called. A constructor is no different.

The UVM factory provides a create() method that you use instead of calling the constructor new() directly. It only passes along one constructor argument, name for uvm_objects, plus a parent argument for uvm_components.