Can two enum member have same value

SystemVerilog
,
1

Looks like system verilog does not allow two enum members to have same value. I got this error on “Enum member ‘YELLOW’ does not have unique value.”
Is there another way?

typedef enum int
{
RED=0,
GREEN=1,
BLUE=2,
YELLOW=2,
WHITE=5
} color;

2

In reply to poojanm2002:

There are many other ways. It would help to know your requirements that led you to think of using enums.

3

In reply to poojanm2002:

Instead of the enum, use the “let”, but enum is better, particularly for debugging using waveforms. Also, for style!


 let RED=0;
 let GREEN=1;

Question: why would you want to have the same values for enum elements?
Ben systemverilog.us