Can systemverilog package with custom data-types be used in VHDL blocks to define Port Types

I am defining a bi-directional port type in system verilog which has a resolution function based on the direction of the port.

For example…
package sv_pack;
class sv_pin;
typedef struct {
real v;
real i;
analog_drive_type drive; //Enumerated object
}

function resolution()
//This sets the value of V/I or monitors VM/IM based on the direction
endfunction

enclass
endpackage

–vhdl port example
Can i import the above system verilog package in VHDL block to define the port type. In the system verilog LRM it says that the data types defined in the system verilog packages can be exported and used by foreign languages.
inout: sv_pin;

Using Questa, you can define a common struct/record type in a package and share that package in both SystemVerilog/VHDL. You can connect input/output ports of these types, but not bidirectional inout ports with reals as SystemVerilog does not yet allow user defined resolution functions to resolve multiple drivers on the same signal.

Ya u can .There is a option where u can connect the System Verilog function with the foreign language.You can use Direct Programming Interface (DPI).

Thanks. Can you share a document or an example how to import a vhdl package which has custom datatypes defined and use it in a system verilog module as a port type.

Also looking at System Verilog LRM 3.1 it should allow 4 state data types to be used for the bidirectional ports. Can you add more to this.

Thanks
Dev

In reply to Dev:

The SystemVerilog 3.1 LRM is over 7 years old; an ancient relic by today’s standards. Please use the IEEE 1800-2009 LRM.

According to section 23.3.3.2, only wires can be used with inout ports, and according to 6.7, SV only allows fized-sized integral data types for wires. So you can’t have a bi-directional port with real data types as you showed in your original example.

The Questa User Manual has a section explaining the mixing of Verilog/VHDL data types in packages.

In reply to dave_59:

I guess your comment is also valid for inout VHDL port defined as an array of a record? right?