Can someone tell me how to pass parameters from module to package

SystemVerilog
,
1

can someone tell me how to pass parameters from module to package.

I am doing like this

package abc;
parameter a = 10;
parameter b = 10;
.
.
endpackage

module abv #(w =10, y = 10) (
input abc::some struct i/p x
) ;
initial
begin
a = w;
b = y;
end
endmodule

the code is just the demo I have not written the whole code.

2

In reply to mukul1996:

That’s not the normal flow of information. Packages are typically the first objects to be compiled, and their parameters get passed to modules and interfaces. What problem are you trying to solve by passing parameters from modules to packages?

3

In reply to sbellock:

While the standard indicates parameters are technically legal within a package, one should only use localparams within a package. And a localparam cannot be modified with a defparam (which would be the only way to modify a package parameter value). You also cannot modify a parameter value procedurally as you’ve shown.

Parameters within packages don’t make sense; one doesn’t explicitly instantiate a package. There’s only one package globally instanced.

From your example - what would the tool do if you had more than one module trying to modify the single package parameter? Who would win the assignment?

I’m not sure why the standards body explicitly allowed parameters within pacakages, but I can’t think of any valid use case.

Regards,

Mark