Hi All,
I am developing decoder portion of my system in system verilog and I have Encoder system available. I want to test my decoder code in modelsim and for that, I have to write testbech to test its functionality. As I have analyzer tool to capture Encoder signals and I can export it into VCD format. So is it possible to use that VCD file as atestbench in modelsim to test mu decoder code? Appreciate your help on this.
Best Regards,
Trupesh Vasoya