Can i ignore one bin and still see how many hits happened?

SystemVerilog
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1

Hi,

I would like to ignore “one” bin but still have the number of bin hits information (That is for debug purposes).
I know that the sense of ignoring the bin is to avoid counting the value. However, it is sometimes interesting to see if something happened even if it is not important. Just for DEBUG purposes or to learn how the stimuli is done.

Systemverilog doesn’t allow you to set an individual option GOAL for a specific bin (you can only set the GOAL for the whole coverpoint/covergroup)so i cannot leave that bin as a “normal bin” because i will have a coverage hole. I have only come to the idea of using ignore_bins, but that doesn’t show the values.

Lets put it in an example.



 cvp_stable_port_configuration_on_P0: coverpoint port0conf {
                bins automode_closed       = {0};
                bins automode_open         = {1};
                bins autoclosemode_closed  = {2};
                bins autoclosemode_open    = {3};
                bins autoclosemode_wait    = {4};
                bins OPEN_phyoff           = {5};
                bins OPEN_phyon            = {6};
                ignore_bins CLOSED_phyoff  = {7};
                bins CLOSED_phyon          = {8};
            }

I would like to see if the CLOSED_phyoff value happened once in the simulation without writing much more code (i could do this if a move that bin to another dummy coverpoint where the goal is zero).
Is it any workaround to see this with the coverage without having a coverage hole?

I also miss to have the simulation sample time of the last bin hit (or n-last sample time). It would be good that SV standard build these debug features in the next standard version.
I can build this feaure by my own creating an array that store last sample simulation time when the condition expression of the bin is satisfied, but again is extra coding for debug features that can be easily automatized. In my opinion, it can be done much more easy introducing new options in coverpoints.
In fact, all this can be easily implemented if SV standard define a new type of bin, The info_bin where each time the bin is sampled there would be a uvm info message,value and time is printed, with verbosity levels. The goal of this info_bin would be always 0, so it doesn’t count for coverage purposes but for debug purposes.

Thanks in advance
Jonathan

2

In reply to Jonathan_Alvarez:

Hi, it seems that you can see in the tool the bin hits for ignore_bins.
As shown in the picture below. The counter on the coverage column will increment on any bin hit. That means, you can still use ignore bins for debug purposes and see if the ignore bins have been triggered.

Regarding knowing the last sample time for a bin i think the best way would be to create a custom uvm_info message for that condition, inside the sample function. Unfortunately, there is no other way to do this without more coding. Alternative, you can use the “illegal_bin” type which will give you an error (no info) with the time of execution.

Note: An interesting paper of what can be done with the time of the first hit of a bin called “FTPT” or First Time Per Test.
http://events.dvcon.org/2015/proceedings/papers/09_3.pdf

Best regards,
Jonathan

3

In reply to Jonathan_Alvarez:
Hi Jonathan,

The intention behind the covergroup feature was to consolidate sample data into a simple in-memory database that is independent of time for analysis after simulation. It was never intended as a verification construct. Tools already provide a lot of debug analysis that is not in the standard (like recording the first hit timestamp). I think it would be difficult to get agreement on what else needs to be recorded and how to present it to the user. There has already been a lengthy discussion over standardized bin naming to get consistent reporting.

You could probably get the some information you are looking for by logging
port0conf to a waveform database, or using the cover directive.

Dave