Can events be passed as an input parameter to module

SystemVerilog
1

Hi,
Hi,
I am trying to pass an event triggered in one module to another.
below is the snippit:

   module top (input bit reset_a
                      bit reset_b
                      bit reset_c);
        event reset_triggered;
        // reset module instance
        reset rst (reset_a,reset_b,reset_c,reset_triggered);

        // register read/write module instance
        reg_rw reg (data, address, rw, reset_triggered);

    endmodule

    module reset (input bit reset_a
                        bit reset_b
                        bit reset_c
                  output event reset_triggered);
        always@(*) begin
            if (reset_a == 1 ||  reset_b == 1) -> reset_triggered
        end
    endmodule

    module reg_rw (output logic [7:0] data,
                   input  logic [3:0] address,
                          bit         rw,
                          event       reset_triggered);
        always@(reset_triggered) begin
        // logic for read and write
        end
    endmodule


Note: This is just an example, the actual code is more complicated.

When i run this i get the below error:

reset rst (reset_a,reset_b,reset_c,reset_triggered));
|
ncvlog: *E,EVNOTR (testbenches/top/top.sv,42|36): An event is not a legal rvalue in this context [9.7.3(IEEE)].

can you please help me with this.
Thanks,

2

In reply to manasa-n:

Can you use struct/logic instead of event and trigger it in always_comb block? This is how RTL modules communicate by event triggers.

// top module
wire reset_triggered; // can be a part of some struct also

// reset module
output logic reset_triggered); // can be a part of some struct also
        always_comb begin
          if (reset_a == 1 ||  reset_b == 1) reset_triggered = 1;
          else  reset_triggered = 0;

// reg_rw module
wire       reset_triggered // can be a part of some struct also

Or if you want to use events explicitly (non-synthesizable way for TB), then declare the event in reg_rw block and trigger from top module using hierarchical access. Triggering point can still come from the reset module.

3

In reply to sharvil111:

Thank you for the reply.
it is for a testbench.
yeah, I would do that but i have around 20 events in my module and having triggering points for these will make my code very bulky and not readable.
is there any way i can pass events as arguments?

i tried it this way but it didn’t work for me

4

In reply to manasa-n:

Contact your tool vendor or try a different simulator.

5

In reply to dave_59:
I am also getting same error " An event is not a legal rvalue in this context [9.7.3(IEEE)]." for below piece of code.

module part (IN, RSEL, OUT);
inout IN;
inout RSEL;
inout OUT;

event trig;
Freq measure_Freq (RSEL, trig);//Instantiation
endmodule 

module Freq (input logic signal, event trigger);
	time t0, t1, timeperiod;
	real freq;//time wont work
	always @(trigger)
	 begin
   	  @ (posedge signal) t0 = $realtime;
    	  @ (posedge signal) t1 = $realtime;
       		timeperiod = t1-t0;
    		freq = 1/timeperiod;
    	  $display("freqams = %t", freq);
  	end
endmodule

@dave_59 / anyone, can you please help me with this error. Thanks!

6

In reply to nixim:
Contact your tool vendor or try a different simulator.

7

In reply to dave_59:

Hi Dave,
Could you tell us whether event as input/output is legal in SystemVerolog LRM or not ?

8

In reply to kitanisi:

The LRM has no restrictions based on data type

Values of all data types on variables and nets can be passed through ports.\

Ports do have restrictions based on signal kind, like only nets can be used for inout ports, and only variables can be used for ref ports. An event can only be used as a variable data type.

9

In reply to dave_59:

Thank you, Dave.
So the error is a bug or restriction of the simulator…