Can anyone suggest me a simple design to verify in-order to learn verification

SystemVerilog
1

I want to build SV Testbench environment and complete verification thoroughly for a couple of simpler designs. Can anyone suggest me a simple design to verify in-order to learn verification.

2

In reply to Ravi421:

There many no. of examples are there in internet(github).

I started my learning from
http://www.testbench.in/
UVM Guide for Beginners – Pedro Araújo for UVM

you can find simple example in respective site.

also always in touch with standard documents from IEEE,Accellera.

i recommend to start with Asynchronous fifo,AMBA3 AHB-lite.