Boundry condition constraint issue

SystemVerilog
1

I need to generate constraint numbers in the following pattern (0,12,24,36,48… but i do not need negative numbers how to generate them?) The below solution does not work. Thank you for the help.

class varc;
  rand int var1;
  constraint c1{ ((var1)%12==0);}
endclass

module tb;
  varc v;
  initial begin
    repeat(20) begin
    v = new;
    v.randomize;
    $display(v);
    end
  end
endmodule
2

In reply to Neal:

I tried this, but not sure if this is the correct way to do it.
Please do help me with another solution.

constraint c1{ (var1)%12==0;var1 inside{[0:2**30]};}
3

In reply to Neal:

If you do not want to see negative numbers, either don’t use signed variables, or add a constraint that they should be greater than or equal to 0.

rand int unsigned var1;

or

constraint positive { var1 >= 0 ; }