Does anyone recommend any books or articles on creating a good Test Plan ?
In reply to VerifEx:
Does anyone recommend any books or articles on creating a good Test Plan ?
From my SVA Handbook 4th Edition
http://systemverilog.us/vf/verification_test_plan.pdf
this page explains the differention between the terms “verification” and “test” and summarizes what goes into a verification plan and a test plan.
I provide complete examples of all of that, including the requirement plans, in that book (see TOC).
There are no real set of rules as to what goes into those documents, and that can vary widely between organizations. What I am baically saying is that this document can be as large as 200 pages, or as few as 5 pages.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115