Hi
In the below Code , the statement(in first initial block) with #3 intra delay blocking is not being printed using monitor statement , which means it is not changing . may i know the reason for it .
EDA playground link : Non blocking statements verilog example - EDA Playground
// Example non blocking simuation
module nonblocking();
reg [2:0] a, b, c ;
// Nonblocking assignments
initial begin
$monitor("%g a=%b b=%b c=%b",
$time,a,b,c);
end
initial begin
a =#3 b + c ;
end
initial begin
b=1 ; c=0 ;
c = #1 b;
#12;
end
endmodule
In reply to rajivdesh:
This is a race condition. The second initial block uses the value of b and c at time 0, which may or may not be assigned by the third initial block.
BTW, do not edit the code on EDAPlayground after you have posted a link to it. Probably not even needed for such a small example.
In reply to dave_59:
Hi Dave
isn’t the c variable is updated from Third initial block and triggers a change in assignment of “a” in second initial block .
In reply to rajivdesh:
There is no triggering/sensitivity in the code you have written. Each initial block starts concurrently at time 0 and proceeds to execute the statements within the begin/end block serially.